Multi-layer stand-alone decompression module for 3rd party Display-Controller IP
Think Silicon’s decompression technology is now also available as a stand-alone IP module, allowing the benefits of its unique compression algorithms to be used with any third-party display controller.
Based on Think Silicon’s framebuffer compression technology (TSC™FB), NEMA®|TSC™ D enables the minimization of the external memory density (or even makes it obsolete). Also, it decreases the number of memory access cycles, lowering the power consumption, while maintaining image quality and extending the battery life of hand-held, wearable and embedded small-display devices.
NEMA®|GPUs employ block-based lossy compression algorithms, allowing 4bpp or 6bpp compression, while using limited silicon area.
The NEMA®|TSC™ D slots in between the 3rd party display controller and the system fabric (AHB/AXI), as illustrated in the figure below (b) and is responsible for decoding the compressed data received and stored in the framebuffer.
Application and Markets
NEMA®|TSC™ D currently supports up to 4 composition layers, compressed or uncompressed (additional layers uncompressed), and can decode data that are compressed with TSC™4 (4bpp) or TSC™6 (6bpp) compression. It supports several output formats and variations (RGBA8888 and all variations on the order of the color components), allowing developers to fine-tune and control the trade-offs between image-quality versus image-size and available memory bandwidth.
NEMA®|TSC™ D Resolution Fully configurable Compression ratio 4bpp 6bpp Compressed Layers Up to 4
NEMA®|TSC™ D is designed for customers, who are using Think Silicon’s NEMA®|GPUs in their SoCs but still want to use a different or existing in-house display controller, exploiting at the same time the advantages of Think Silicon’s patented TSC™ “Compression-Decompression” Technology.
By decoupling the decompression-module from Think Silicon’s own display controller (NEMA®|dc), Think Silicon offers to its customers more flexibility when designing their SoC project.
NEMA®|TSCTM D can be customized at design-time choosing from a number of configuration options that enable or disable features of the design. Additionally, several features (e.g. layer formats) can be selected dynamically at run-time through the software.
The NEMA®|TSCTM D is available in Verilog and easy to integrate and verify. NEMA®|TSCTM D is designed with AMBA interfaces. The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables and Documentation
Deliverables include: complete set of synthesis, STA (Static Timing Analysis) scripts, OS drivers for Linux, Android, FreeRTOS, and portable bare drivers.
Documentation includes: IP manual, integration manual, software-library manual, application notes.
- AMBA AHB 32-bit
- AMBA AXI4 32/64-bit interfaces for easy SoC Integration
- TSCTM Compressed framebuffer support
- Multiple layer display controller support
- Compression schemes
- Layer Overlay
- Number of layers (up to 4 compressed, additional uncompressed)
- Master Interface
- AMBA AHB 32bit
- AMBA AXI4 32/ 64bit
- Slave Interface
- AMBA AHB, AXI4-Lite
The software package includes Baremetal and OS drivers for Linux. The module interacts with the rest of the system via two memory-mapped interfaces and is software configurable with regards to a host of parameters. The software development kit also includes NEMA®|Pix-Presso, a utility for converting several images to formats (16 & 32-bit RGB w/wo transparency, grayscale, transparency-only, png, jpeg, etc.) suitable for low power embedded devices.
- OS support
- RTOS (Baremetal)
- Software Development Kit
- OS support
High quality compression is demonstrated in the following video.